1. Field of the Invention
The invention relates to a deep trench self-alignment process, and more particularly to a deep trench self-alignment process for an active area of a partial vertical cell and a method for fabricating the same.
2. Description of the Related Art
There is much interest in reducing the size of individual semiconductor devices to increase their density on an integrated circuit (IC) chip. This reduces size and power consumption of the chip, and allows faster operation of the chip. In order to achieve a memory cell with a minimum size, the gate length in a conventional transistor must be reduced to decrease the lateral dimension of the memory cell. However, the shorter gate length results in higher leakage current that cannot be tolerated, and the voltage on the bit line must therefore also be scaled down. This reduces the charges stored on a storage capacitor, thus requiring a larger capacitance to ensure that stored charges are accurately detected.
In order to solve the above-mentioned problems, a stacked capacitor and a deep trench capacitor have been developed for a high-integration memory cell, such as dynamic random access memory (DRAM) cell. Specifically, the deep trench capacitor is formed in a deep trench within the silicon substrate, such that the capacitor storage region does not take up any additional wafer area. In addition, a vertical transistor has recently been developed which can maintain gate length of a suitable value to reduce leakage without decreasing the bit line voltage or increasing the memory cell's lateral dimensions.
A type of vertical transistor with a deep trench capacitor is disclosed in U.S. Pat. No. 6,034,389.
FIGS. 1a to 1e are cross-sections of the conventional method for fabricating a floating gate of a split gate flash memory.
In FIG. 1a, a P-type silicon substrate 101 comprises a plurality of deep trenches 104 and a plurality of pillars 102 corresponding to the deep trenches 104.
A thin pad oxide layer 103a and an oxynitride layer 103b are sequentially formed on the surface of the pillar 102. A doped oxide layer 105, such as ASG, acting as a source region diffusion source is formed on a bottom sidewall of the deep trench 104. The doped oxide layer 105 is annealed at a high temperature and a short time to diffuse As ions into the sidewall of the pillar 102 to form an n+ type diffusion region acting as an n+ type source region 106.
In FIG. 1b, the doped oxide layer 105 is removed.
In FIG. 1c, an ONO thin film 107 is formed on the sidewall of the deep trench 104 acting as a dielectric material of the deep trench capacitor. An n+ type poly layer 108 is formed in the deep trench 104 acting as a capacitor plate. The ONO thin film 107 and the capacitor plate 108 are etched to a predetermined depth.
In FIG. 1d, a shelter 109 is formed on the n+ poly layer 108 acting as a gate insulator. A gate oxide layer 110 is formed on the sidewall of the deep trench 104, and the deep trench 104 is filled with an n+ poly layer 111 acting as a control gate.
In FIG. 1e, the control gate 111 is separated into word lines by etching. The thin pad oxide layer 103a and oxynitride layer 103b are removed. An n+ drain 112 is formed in the top of the pillar 102. A metal layer is formed acting as a bit line layer 113. Thus, a memory unit array is completed.
According the above-described memory cell, the n+-type polysilicon layers 111, the n+-type source region 106 and the n+-type drain region 112 form the vertical transistor, and the n+-type source region 106, the ONO thin film 107 and the n+-type polysilicon layers 108 form the deep trench capacitor. In an open bit line case as described, the storage node of the deep trench capacitor is common to all the memory cells in the array, and the charge is stored on the n+-type source region 106 within each pillar 102.
Although a channel occurs in the pillar 102 between n+ source region 106 and n+ drain region 112, the width of the pillar 102 cannot be reduced to avoid the depletion regions overlapping adjoining source regions 106 on the sidewall of the pillar 102.
The dopant in the capacitor easily diffuses to the active area when the active area in the pillar 102 is misaligned with the deep trench 104. The electrical properties of the memory cell are affected by the dopant concentration of the active area.